1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and relates to, e.g., an electrically rewritable NAND type EEPROM (electrically erasable and programmable ROM) provided with memory cells each having a control gate and a floating gate.
2. Description of the Related Art
In recent years, as an electrically rewritable non-volatile semiconductor memory device, an NAND type EEPROM has been known. The NAND type EEPROM is characterized in that selection gate transistors arranged at both ends of a plurality of memory cells (which will be referred to as NAND cells hereinafter) connected in series determine selection and non-selection of each NAND cell.
When selection of each NAND cell is performed by using the selection gate transistors, each memory cell does not have to have a signal ratio in a selective state or a non-selective state. This is an influential factor which advances miniaturization of each memory cell in the NAND type EEPROM but, on the other hand, miniaturization of the selection gate transistor has not been greatly advanced.
It is to be noted that an NAND type EEPROM provided with a program control circuit which controls a voltage supplied to each gate of NAND cells and selection gate transistors has been disclosed as a prior art concerning the present invention (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 9-82922). However, the selection gate transistors cannot be miniaturized even in this NAND type EEPROM.